"Pure Power" (more accurate power monitoring sensors).PTE (page table entry) coalescing, which combines 4 kiB page tables into 32 kiB page size.Support for the SMAP, SMEP, XSAVEC/XSAVES/XRSTORS, XSAVES, CLFLUSHOPT, and CLZERO instructions.RDSEED support, a set of high-performance hardware random number generator instructions introduced in Intel's Broadwell microarchitecture.Move elimination, a method that reduces physical data movement to reduce power consumption.A dedicated stack engine for modifying the stack pointer, similar to that of Intel Haswell and Broadwell processors.The branch predictor is decoupled from the fetch stage.Improved branch prediction using a hashed perceptron system with Indirect Target Array similar to the Bobcat microarchitecture, something that has been compared to a neural network by AMD engineer Mike Clark.Close to 2× faster L1 and L2 bandwidth, with total 元 cache bandwidth up 5×.Each SMT core can dispatch up to six micro-ops per cycle (a combination of 6 integer micro-ops and 4 floating point micro-ops per cycle).Newly introduced "large" micro-operation cache.Four ALUs, two AGUs/load–store units, and two floating-point units per core.Processors with more than four cores consist of multiple CCXs connected by Infinity Fabric. A fundamental building block for all Zen-based CPUs is the Core Complex (CCX) consisting of four cores and their associated caches.This is a feature previously offered in some IBM, Intel and Oracle processors. SMT (simultaneous multithreading) architecture allows for two threads per core, a departure from the CMT (clustered multi-thread) design used in the previous Bulldozer architecture.The L1 cache has been changed from write-through to write-back, allowing for lower latency and higher bandwidth.This SoC design allows the Zen microarchitecture to scale from laptops and small-form factor mini PCs to high-end desktops and servers.Īccording to AMD, the main focus of Zen is on increasing per-core performance. This has advantages in bandwidth and power, at the expense of chip complexity and die area. The memory, PCIe, SATA, and USB controllers are incorporated into the same chip as the processor cores. But not all Socket AM4 CPUs are based on Zen microarchitecture (the 7th gen APUs and Athlon X4s are based on Excavator microarchitecture). Zen processors use three different sockets: desktop and mobile Ryzen chips use the AM4 socket, bringing DDR4 support the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 RAM and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the TR4 socket and Epyc server processors offer 128 PCI 3.0 lanes and octal-channel DDR4 using the SP3 socket. The cache system has also been redesigned, making the L1 cache write-back. SMT has been introduced, allowing each core to run two threads. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and can execute significantly more instructions per cycle. Zen is a clean sheet design that differs from the long-standing Bulldozer architecture. The first Zen-based CPUs codenamed "Summit Ridge" reached the market in early March 2017, Zen-derived Epyc server processors launched in June 2017 and Zen-based APUs arrived in November 2017. The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. Zen is the codename for a computer processor microarchitecture from AMD, and was first used with their Ryzen series of CPUs in February 2017.
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